A metal silicide layer is formed on the surface of a source region, a drain region, and/or a gate electrode of a semiconductor device to reduce resistance. The metal silicide layer may be formed by depositing a metal layer on a silicon layer and by annealing the metal layer and the silicon layer, where the metal layer and the silicon layer react to form the metal silicide layer.
However, as the size of the semiconductor device or chip continues to get smaller, two adjacent silicide layers on two neighboring gate electrodes may come close together, thus creating a short circuit between the neighboring gate electrodes. To avoid the problem, the thickness of the metal layer used to form the metal silicide layer can be reduced. However, the thin metal layer used to form the metal silicide layer can cause an uneven surface or a breakage of the metal silicide layer, thus causing an unexpected variation of the resistance in the metal silicide layer.